A conventional example of a method of testing data (e.g., code) in a circuit under test [e.g., a ROM (Read-Only Memory), etc.] mounted on a semiconductor integrated circuit (e.g., a single-chip microcomputer) is as follows: On the basis of an address signal (one synchronized to a clock signal) that has been output in parallel from a CPU (Central Processing Unit) when a test mode (ROM dump test mode) is in effect, the code (synchronized to the clock signal) of the corresponding address is read out of the ROM in parallel, the code that has been read out is output (in parallel) to the exterior of the semiconductor integrated circuit, and the code that has been output is tested by an LSI (Large-Scale Integration) tester (not shown). Another method mounts a MISR (Multiple-Input Feedback Shift Register), which compresses and serially outputs the code that has been output from a ROM, on the semiconductor integrated circuit, and uses an LSI tester (not shown) to test the compressed code that has been serially output [see FIG. 7, e.g., FIG. 5(C) of Patent Document 1]. With this method, the code that has been output from the semiconductor integrated circuit is synchronized to the clock signal and compared with an expected value in the LSI tester, whereby the circuit is tested to determine whether the code is correct or not.
Since the speed of ROM read-out also is tested in the above-described method, the clock signal input to the semiconductor integrated circuit from the LSI tester has a frequency that is the maximum operating frequency of the ROM. Since the code that is output from the semiconductor integrated circuit to the LSI tester also is synchronized to this clock signal, it also has a frequency identical with the maximum operating frequency of the ROM. Also, in a case where a semiconductor integrated circuit having a mounted MISR is tested, the clock signal (CLK) supplied to the MISR is a single-channel signal. If code compression and serial output are performed by the MISR based upon a single-channel high-frequency clock signal, then the compressed data signal that is output from the MISR also will be a high-speed signal.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2000-137061A [FIG. 5(C)]